The invention relates to a semiconductor memory device comprising a source zone located at a surface of a semiconductor body, a memory gate located beside the source zone and insulated from the surface, by means of which a potential well can be induced in the semiconductor body, in which well an information-representing charge packet in the form of a quantity of charge carriers supplied by the source zone can be stored, and a switching gate located between the source zone and the memory gate and insulated from the surface, by means of which the connection between the source zone and the potential well can be closed or interrupted. Such a semiconductor memory device may be, for example, a charge transfer device, such as a CCD or a BBD, whose input stage is constituted by the said source zone, the said switching gate and the said memory gate. When a positive voltage is applied to the memory gate (in the case of an n-channel CTD), a potential well is generated in the subjacent part of the channel. When a positive voltage is also applied to the switching gate, the channel below the switching gate becomes conducting, as a result of which electrons can flow from the n-type source zone (in the case of an n-channel CTD) into the potential well below the memory gate. When the voltage at the switching gate is reduced, the connection between the source zone and the charge below the switching gate is interrupted, as a result of which an insulated charge packet is formed below the memory gate, which represents, for example, a "1" in the case of digital signals. This input method, designated as "diode cut-off method", is described inter alia in the book "Charge Coupled Devices and Systems" by Howes and Morgan, ed Wiley and Sons, 1980, pp. 111-115.
As is well known, a signal which is introduced into the memory can be distorted by all kinds of interference influences, as a result of which the signals arriving at the output will deviate more or less from the nominal values "1" and "0". During the detection, in general the value "1/2" halfway between the "1" level and the "0" level is used as a reference. If the signal lies above 1/2, it is considered as a "1", whereas if it lies below 1/2, it is considered as a "0". This means that the interference margin (i.e. the maximum permissible interference with which the signal can still be correctly detected) is half or 50% of the distance between the nominal "1" and "0".
For forming the potential well below the memory gate, it is common practice to apply to the memory gate a voltage of +5 V, which can be directly derived from the supply source. As will be explained more fully hereinafter, the fluctuations in the supply voltage in combination with the input method described above can give rise to problems.
The permissible fluctuations in the supply voltage are normally about 10%, that is to say that the clock voltage applied is not always exactly 5 V, but may vary between 5.5 V and 4.5 V. This variation also occurs with the clock voltage applied to the clock electrodes during the transport of the charge packet. The consequence of the fluctuation of the voltage at the memory gate at the input will be that the size of the charge packet will also vary. Since overflow of the charge from one packet (bit) to another bit will lead to disturbing errors, the filling level below the said memory gate must be such that, when this well is filled at the maximum supply voltage, overflow does not yet occur even at the minimum supply voltage. This can be achieved in that the potential well is filled up to 80% of the supply voltage. At a supply voltage of 5.5 V, the potential well is then filled up to a level of 4.4 V. At a supply voltage of 4.5 V, the well is filled, however, only up to a level of 3.6 V. This means that the fluctuation in the supply voltage in this input method also gives rise to a fluctuation of about 10% in the size of the charge packet, which corresponds to an interference of 20%. Therefore, 20% of the permissible interference margin of 50% is used by the fluctuations of the supply voltage. Since other interference sources exist in addition to the supply voltage fluctuations, such as leakage current, incomplete charge transport, capacitive crosstalk between the electrodes, and output amplifier interference, it is desirable to reduce the influence of the interferences in the supply voltage.
An analogous problem may also arise in other memories, for example, in 1 MOS bit dynamic memories. In these memories, each memory cell consists of a capacitor, in which information is stored in the form of charge, and of an insulated gate field effect transistor. The capacitor, or at least the information-containing plate of the capacitor, is connected to the source or the drain of the transistor. The other main electrode of the transistor is connected to a bit line, through which information is written or read. The gate electrode of the transistor is connected to a word line. Just like in a CCD, the memory capacitor comprises a gate electrode, which is insulated from the surface of the semiconductor body by a thin dielectric and by means of which a potential well is induced in the semiconductor body, in which well a charge packet is stored as information. In order to keep the surface area of the chip as small as possible, the memory capacitors are made as small as possible. Since consequently the storage capacity becomes very small, also with these devices it is of great importance to make the influence of the interferences in the supply voltage applied to the memory gate as small as possible.